The present invention generally relates to semiconductor manufacturing and more particularly to wafer bonding techniques as part of three-dimensional (3D) integration processes.
In a 3D integration process individual wafers may be stacked and joined into a single package in order to reduce space. A common technique used in wafer-scale 3D integration is wafer bonding. In a wafer bonding process, the electronic devices on one wafer may be aligned with the electronic devices on another wafer, and then the wafers may be bonded together using, for example, an oxide-oxide fusion bonding process.